module fsm_seq(rst,clk,x,z,state);
input x,clk,rst;
output z;
output [2:0] state;
reg [2:0] state;
reg z;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;
always @(posedge clk)
begin 
	if(rst)
	begin state<=s0;z<=0; end
	else
	case(state)
	 s0:begin
			if(x==1) begin state<=s1; z<=0;end
			else     begin state<=s0; z<=0;end
		end
	 s1:begin
			if(x==1) begin state<=s1; z<=0;end
			else     begin state<=s2; z<=0;end
		end
	 s2:begin
			if(x==1) begin state<=s3; z<=0;end
			else     begin state<=s0; z<=0;end
		end
	 s3:begin
			if(x==1) begin state<=s1; z<=0;end
			else     begin state<=s4; z<=1;end
		end
	 s4:begin
			if(x==1) begin state<=s3; z<=0;end
			else     begin state<=s0; z<=0;end
		end
	default:state<=s0;
	endcase
	end
endmodule
